The present invention generally relates to circuit design and specifically relates to software used to model timing of circuits or the minimum time delay through a static gate.
Systems are presently known that use the information provided in netlists to evaluate circuit timing and other related parameters. More specifically, systems are known that perform a timing analysis of circuits using netlist files. Although the operational specifics may vary from system to system, generally such systems operate by identifying certain critical timing paths, then evaluating the circuit to determine whether timing violations may occur through the critical paths. As is known, timing specifications may be provided to such systems by way of a configuration file.
One existing system is marketed under the name PATHMILL(copyright), by Synopsys, Inc. PATHMILL(copyright) is a transistor-based analysis tool used to find critical paths and verify timing in semiconductor designs. Using static and mixed-level timing analysis, PATHMILL(copyright) processes transistors, gates, and timing models. It also calculates timing delays, performs path searches, and checks timing requirements. PATHMILL(copyright) may analyze combinational designs containing gates, and sequential designs containing gates, latches, flip-flops, and clocks. Combinational designs are generally measured through the longest and shortest paths.
While tools such as these may be useful for the design verification process after layout, there are various shortcomings in the PATHMILL(copyright) product and other similar static timing analyzer products. For example, there is often a need to identify certain logic gates or particular combinations of logic gates. PATHMILL(copyright) may be configured to evaluate a netlist file and identify certain nodes but does not automatically identify certain configurations that may prove troublesome.
The present invention is directed to a method for evaluating a circuit design to identify potential race conditions including the steps of identifying switching elements in a design; storing switched node pair and control node information for each of the switching elements; identifying stacks of the switching elements; storing information about the stacks of switching elements; identifying parallel connected ones of the switching elements; identifying parallel stacks; and calculating a combined switching current for the parallel switching elements and stacks.